The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including at least one tilted semiconductor nanowire which can provide a longer gate length than a horizontal semiconductor nanowire at a same gate pitch. The present application also relates to a method of providing such a tilted semiconductor nanowire structure.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor nanowire field effect transistors (FETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor nanowire field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In its basic form, a semiconductor nanowire FET includes a source, a drain and one or more nanowire channels between the source and the drain. A gate electrode, which contacts the one or more nanowire channels, regulates electron flow through the nanowire channel between the source and drain. Semiconductor nanowires that are oriented vertically or horizontally relative to an underlying substrate are known.
Scaling the gate length in aggressively scaled contacted gate pitch is challenging for 5 nm and beyond technologies, since there is not much room left for the gate length. Nanowire width scaling results in considerable mobility reduction, and an access resistance increase, which are not very desirable.
There is thus a need to provide a semiconductor nanowire structure that has a longer gate length than horizontally oriented semiconductor nanowires at the same pitch.